Embodiments of the disclosure relate to the field of semiconductor device fabrication. In particular, embodiments of the disclosure relate to a flash memory device and method of manufacturing the same.
With the continuous development of semiconductor technology, the feature sizes of semiconductor devices continue to decrease. However, in a memory device, such as a NAND-type nonvolatile memory device, the capacitance between gate lines (i.e., word lines) greatly affect the performance of the memory device. A conventional semiconductor manufacturing process utilizes an interlayer dielectric layer to isolate the gate lines. However, such approach results in higher capacitance between the gates, thereby affecting the performance of the device.
Thus, there is a need for a novel semiconductor structure and manufacturing method for reducing capacitance between gate lines.